1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method. More specifically, the present invention relates to a semiconductor device and fabrication method including an amorphized source to improve hot-carrier reliability.
2. Description of the Related Art
Hot-carrier effects cause unacceptable performance degradation in MOSFET devices built with conventional drain structures when channel lengths are short. As the dimensions of MOSFET devices are reduced and the supply voltage remains constant or is not reduced as rapidly as the structures are reduced in scale, the lateral electric field in the channel increases. Increases in the lateral electric field cause acceleration and heating of inversion-layer charges, resulting in multiple harmful device phenomena, called "hot-carrier" effects. A particularly destructive hot-carrier effect is damage to the gate oxide or the silicon-oxide interface of a device leading to time-dependent degradation of various MOSFET characteristics including threshold voltage V.sub.T, linear region transconductance g.sub.M, subthreshold slope S.sub.t, saturation current I.sub.dsat, and ultimately device lifetime.
Hot-carrier degradation is reduced by decreasing the magnitude of the maximum channel electric field .epsilon..sub.ymax located at the drain end of the channel and by separating the maximum current path in the channel from the location of the maximum electric field location. Reduction of the maximum channel electric field .epsilon..sub.ymax and separation of the maximum current path are achieved by modifying the structure of a MOSFET using special drain field-reducing structures and by increasing the resistance of the gate oxide and silicon-oxide interface to hot-carrier degradation through the use of special processing techniques.
A common modified MOSFET structure for reducing hot-carrier effects is called a lightly doped drain (LDD) structure in which a lightly doped (n.sup.-) buffer region is formed between a heavily arsenic-doped (n.sup.+) drain and the channel, outside of the channel. The drain is formed by two implants including a first implant self-aligned to the gate electrode and a second implant self-aligned to the gate electrode and sidewall spacers formed lateral to the gate electrode. Accordingly, the MOSFET includes a drain with a graded or lightly-doped extension. The maximum channel electric field .epsilon..sub.ymax is reduced by forming this buffer region because the maximum electric field in a reverse-biased pn junction is highest when the junction is abrupt. In the lightly doped drain (LDD) structure, an abrupt drain doping profile is replaced by a more gradually decreasing, or graded, profile so that the voltage drop is shared by the drain and the channel.
However, in many cases LDD devices have been unable to improve or even attain the same hot-carrier reliability as conventional single-drain MOSFETs. The poor performance of early LDD devices resulted from an erroneous or incomplete understanding of the electrical behavior of the LDD structure. For example, reduction of maximum channel electric field .epsilon..sub.ymax was considered to be of fundamental importance for improving hot-carrier reliability. However, it was subsequently determined that other parameters including the spatial location of the .epsilon..sub.ymax point, the spatial offset of the lightly doped dose from gate edge, the thermal budget following the lightly doped drain implant, doping concentrations within the channel, and the like are important for determining MOSFET behavior. In particular, it has been determined that hot-carrier resistance is optimized using an LDD structure in which the heavily doped n.sup.+ region is located at the edge or just under the edge of the gate, and the lightly-doped n.sup.- region should be located entirely under the gate. Unfortunately, this optimum structure is difficult to fabricate. Specifically, attaining full lightly-doped n.sup.- overlap using an oxide-spacer-based LDD design requires the use of a very narrow spacer in combination with a substantial thermal drive-in. Unfortunately, in submicron CMOS technologies, such a combination causes the source/drain junctions in both NMOS and PMOS transistors to be too deep to control short-channel effects.
Several approaches have been developed for improving the characteristics of an LDD MOSFET. First, the doping concentration in the lightly doped n.sup.- region of the LDD structure is increased to improve the drive-current capability and reduce a "structural degradation effect" that degrades the hot-carrier lifetime of a conventional LDD MOSFET. Second, the vertical profile of the lightly doped n.sup.- region is modified to steer a current path away from the surface of the MOSFET and to separate the location of .epsilon..sub.ymax and the path of maximum current flow in the MOSFET. Third, dopants are selectively implanted beneath the lightly doped n.sup.- region to reduce the susceptibility of submicron LDD structures to short-channel effects
What is needed is a technique for fabricating MOSFET devices that substantially improves hot-carrier reliability while maintaining fabrication simplicity. What is further needed is a semiconductor fabrication method that retards diffusion of ions in source/drain regions.